The calculation of a composite vector with two quadrature signals is used in various fields. For example, in a spread-spectrum communication system receiver using Quadrature Phase Shift Keying (QPSK), the absolute-value of a complex number comprising I channel and Q channel signals is calculated as shown in formula (1) so as to judge whether the despreaded signal is at the correlation peak. ##EQU2## In formula (1), Mag is the absolute-value of a complex number.
Usually, such calculations are performed by a DSP (Digital Signal processor) using approximation formulas. For example, Stanford Telecom in the United Slates developed a highly-rated digital LSI for calculating approximate values in formula (2): EQU Mag=Max{Abs(I),Abs(Q)}+1/2Min{Abs(I), Abs(Q)} (2)
In formula (2), Max { } id the maximal value, Min { } is the minimal value, and Abs( ) is the absolute-value.
The inventors have proposed various analog operation circuits and filter circuits that feature low electric power consumption, high speed and high accuracy.
FIG. 15(a) shows the fundamental structure of an analog operation circuit (hereinafter, neural computation circuit). In FIG. 15(a), V1 and V2 are input terminals, Vo is an output terminal, and Amp is an inverting amplifier. In Amp, utilizing the part changing the outputs of CMOS inverters from a high level to a low level or from a low level to a high level, inverters form an amplifier comprising CMOS inverters serially connected in an odd number of stages, three such inverters 111, 112 and 113, being shown.
Input capacitor C1 is provided between and serially to V1 and point B at the input of Amp, and input capacitor C2 is provided between and serially to V2 and B. Feedback capacitor Cf is connected between Vo and B.
Registers R1 and R2 are provided to control the gain of the amplifiers, and capacitor Cg is provided to adjust the phase. Both of them prevent oscillation within Amp.
In a circuit with such a structure, as the voltage amplifying ratio of Amp is very large, the voltage at B is approximately constant and assumed to be Vb. Point B is connected to C1, C2, Cf and the gate of the transistor which structures 111, and B is also floating from every source voltage.
When the electric charge stored in each capacitor in the initial state is 0, the total charge stored in each capacitor referencing B is 0, even after V1 and V2 are input. From this, formula (3) is true: EQU C1(V.sup.1 -Vb)+C2(V2-Vb)-Cf(Vo-Vb)=0 (3)
The dynamic range is made maximal by setting the voltage Vb at B to be half of the source voltage. Therefore, Vb is set to be Vdd/2 when the source voltage is supplied by +Vdd and ground (0V), and Vb is set to be 0 when the source voltage is plus and minus. Here, it is assumed that the source voltage is +Vdd and ground, and Vb=Vdd/2. Accordingly, formula (4) is derived from formula (3): ##EQU3##
Output Voltage Vo is output from the neural computation circuit. Vo has an offset voltage of ((C1+C2+Cf)/2Cf)Vdd, and its voltage is the sum of V1 and V2 after multiplying C1/Cf and C2/Cf, respectively, with inverted polarity. The offset voltage can be easily deleted by providing voltage to cancel it to the output of Amp through a capacitor. A weighted addition circuit for adding a plurality of weighted input signals can thus be formed.
Also, a subtraction circuit can be structured by connecting two addition circuits in series, then providing positive inputs to the former and negative inputs to the latter.
Further, an addition circuit for the control signals and input analog signals can be structured by changing the size of input capacitors C1 and C2 according to the control signals.
Although there are two input terminals (V1 and V2) in this embodiment, any number of input terminals can be adopted.
As stated above, various computation circuits can be constructed from neural computation circuits, which require very low electric power consumption and operate at high speeds because they are driven only by the electric voltage. The capacitor size is determined by the conductor area on a semiconductor substrate: this area can be precisely controlled, and very accurate computation circuits realized.
To simplify, FIG. 15(b) is used instead of FIG. 15(a).
Circuits with such analog architecture have problems contrary to digital LSIs like the above DSP, because operations are performed by analog voltage.
Therefore, a complex absolute-number calculation circuit is proposed for analogously calculating vector absolute-value by formula (2) or the improved formula of Japanese Patent Application No. 7-274839.
FIG. 16 shows an exemplary block diagram of the proposed complex absolute-value calculation circuit.
In FIG. 16, 121 shows an input terminal for receiving the signal of component I corresponding to the real part of a complex number, 122 shows an input terminal for receiving the signal of component Q corresponding to its imaginary part, 123 shows the first absolute-value calculation circuit for outputting the absolute-value Abs (I) of component I input from terminal 121, and 124 shows the second absolute-value calculation circuit for outputting the absolute-value Abs (Q) of component Q input from input terminal 122. Number 125 shows a subtraction circuit for outputting the difference between the output of 123 and that of 124 (Abs(1)-Abs(Q)), 126 shows the third absolute-value calculation circuit for outputting, the absolute-value of the output of 125 (Abs(Abs(1)-Abs(Q)), and 127 shows an addition circuit for adding outputs from 124 and 126 with weighting. As shown, the outputs of 123, 124 and 126 are weighted with values b, c and a, respectively.
Neural computation circuits are used in absolute-value calculation circuits 123, 124 and 126, subtracting circuit 125 and addition circuit 127.
Circuits 123, 124 and 126 have the same structure which FIG. 17 shows. In FIG. 17, 131 shows an input terminal for receiving analog signal voltage Vin, and 137 shows an output terminal for outputting signals corresponding to the absolute-value of Vin (Vin!).
Number 132 shows an input capacitor C1, 133 shows a feedback capacitor Cf, and 134 shows the inverting amplifier above. These include the neural computation circuit. As the ratio of 132 and 133 is 1 (C1=Cf), the output voltage of inverting amplifier 134 is the signal voltage Vin (Vdd-Vin) input from 131.
Number 135 shows an inverter circuit, structured like a CMOS. Threshold voltage Vth is half the source voltage Vdd, that is, Vth=Vdd/2. Therefore, when input signal voltage Vin is equal to or greater than Vdd/2, the output level is low (0V), and when input signal voltage Vin is lower than threshold voltage Vth, the output level is high (Vdd). This means inverter 135 functions as a comparator for comparing input signal voltage Vin with voltage Vdd/2.
Number 136 shows a multiplexer including a pair of CMOS transmission gates. When the output of 135 is a low level, the output from 134 (Vdd-Vin) is selected and output to 137, and when the output of 135 is a high level, input signal Vin is output from output terminal 137 as it is.
This absolute-value calculation circuit outputs Vdd-Vin when Vin.gtoreq.Vdd/2, and it outputs Vin when Vin&lt;Vdd/2. Referencing Vdd/2, input signal Vin is output, which has a higher level than the reference level, and is inverted in the direction lower than the reference voltage; that is, the output signal is the inverted absolute-value having the reference level Vdd/2 of the input signal.
Assuming weighted coefficients a=5/22 and b=c=15/22 in addition circuit 127, the complex number absolute-value Mag calculated by approximation formula (5) is output from output terminal 128: ##EQU4##
Formula (5) calculates approximate values more precisely than formula (2). When a, b and c are changed into other values and used in the approximation formulas, any vector absolute-value can be calculated.